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cryptography ip-cores in vhdl / verilog
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cryptocores/des/sim/verilog
T. Meissner cb14f089b9 add acceptin & acceptout ports 9 years ago
..
data_input.txt added test data for decryption test cases 11 years ago
data_output.txt added test data for decryption test cases 11 years ago
key_input.txt added test data for decryption test cases 11 years ago
makefile dependency files now moved into 2 variables SRC_FILES & SIM_FILES 11 years ago
tb_des.tcl add acceptin & acceptout ports 9 years ago
tb_des.v added test cases for decryption in stimuli & checker; bugfix wwith validout detection 11 years ago