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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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88
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
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T. Meissner
ccf8140132
complete refactoring of the des verilog code
* now 2 seperate processes: key scheduling & data path * keys are now concurrent wire assignments
12 years ago
aes
new verily version of ads, startup code only at the moment
13 years ago
cbcdes
remove OVL support in older, finished & verified projects
13 years ago
cbctdes
remove OVL support in older, finished & verified projects
13 years ago
des
complete refactoring of the des verilog code
12 years ago
tdes
remove OVL support in older, finished & verified projects
13 years ago