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formal_hw_verification
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1 Commits (master)

Author SHA1 Message Date
  T. Meissner 3d57fff226 Replace reset checks by async VHDL asserts; Add assumptions about inputs 5 years ago
  T. Meissner f2f433b165 Use PSL functions instead of workarounds; add forgotten always to asserts in alu 6 years ago
  T. Meissner 6c3a6db83b Remove unused SVA properties file; Makefile optimizations; use prep auto-top option to prevent error with not founded top-level module 7 years ago
  T. Meissner bd5fcbcb7a GHDL supports memory with resets, finally 7 years ago
  T. Meissner e71b70d34e Add Assumptions about job req VAI interface 7 years ago
  T. Meissner 8cf0be6e4c Add many new asserts & covers 7 years ago
  T. Meissner 195765a2aa Adapt to use GHDL as plugin for Yosys VHDL synthesis 7 years ago
  T. Meissner b48e99c1f0 Simplify signal generation 8 years ago
  T. Meissner 4e30f44cb0 Fix req cai handling; add more properties 8 years ago
  T. Meissner 63fc34f66a Add DoutValid_o to condition for state change in putput states 8 years ago
  T. Meissner a0f6a0b81d Add simple VAI register file as base to try to formal verify FSM designs 8 years ago