Trying to verify Verilog/VHDL designs with formal methods and tools
vhdl
verilog
systemverilog
sva
assertions
formal
yosys
T. Meissner ac767bb9d3 Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability 6 months ago
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Makefile Makefile: add clean target; fixed Reset_n_i port dir in alu_t.sv 8 months ago
alu.vhd Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability 6 months ago
alu_f.sby Data in/put width now unconstrained 7 months ago
alu_t.sv Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability 6 months ago