11 Commits (master)

Author SHA1 Message Date
  T. Meissner 3d57fff226 Replace reset checks by async VHDL asserts; Add assumptions about inputs 3 years ago
  T. Meissner f2f433b165 Use PSL functions instead of workarounds; add forgotten always to asserts in alu 4 years ago
  T. Meissner bc59bfd47c Symplifing Makefile targets 4 years ago
  T. Meissner 3e621b02e9 Add alu checks 4 years ago
  T. Meissner d420b00310 Making alu design work with GHDL synthesis 4 years ago
  T. Meissner ac767bb9d3 Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability 5 years ago
  T. Meissner 7aa4aa52a8 Data in/put width now unconstrained 5 years ago
  T. Meissner 12e20b1da2 Some small improvements 5 years ago
  T. Meissner fca663d7ac Makefile: add clean target; fixed Reset_n_i port dir in alu_t.sv 5 years ago
  T. Meissner 2f7959db61 Remove gitignore from alu folder; added link to Yosys 5 years ago
  T. Meissner 4feec0fff6 Inital commit 5 years ago