formal_hw_verification

324 KiB

Branch: master

Author	SHA1	Message	Date
T. Meissner	3d57fff226	Replace reset checks by async VHDL asserts; Add assumptions about inputs	4 years ago
T. Meissner	f2f433b165	Use PSL functions instead of workarounds; add forgotten always to asserts in alu	5 years ago
T. Meissner	bc59bfd47c	Symplifing Makefile targets	5 years ago
T. Meissner	3e621b02e9	Add alu checks * Add asserts for correct behaviour of Overflow flag * Switch to smtbmc engine in prove mode (much faster than abc)	5 years ago
T. Meissner	d420b00310	Making alu design work with GHDL synthesis * Remove unused SVA properties file * Makefile optimizations * Use prep auto-top option to prevent error with not founded top-level module * Rewrite assignments of Dout_o & Overflow_o as GHDL synthesis don't support concatenation on left side of assignments * Add some simple PSL assertions	5 years ago
T. Meissner	ac767bb9d3	Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability	6 years ago
T. Meissner	7aa4aa52a8	Data in/put width now unconstrained	6 years ago
T. Meissner	12e20b1da2	Some small improvements * Adopt init state generation for initial reset constraining * Add assume about inactive reset after initial active * Replaced OPC consts by macros * Replace SVA reset check by simple unclocked immediate assertion	6 years ago
T. Meissner	fca663d7ac	Makefile: add clean target; fixed Reset_n_i port dir in alu_t.sv	6 years ago
T. Meissner	2f7959db61	Remove gitignore from alu folder; added link to Yosys	6 years ago
T. Meissner	4feec0fff6	Inital commit	6 years ago

11 Commits (master)