Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

T. Meissner 38ae7057c2 Incomment proof with abc pdr		6 years ago
alu	Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability	6 years ago
counter	Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability	6 years ago
dlatchsr	Add example for dlatchsr error	6 years ago
vai_reg	Incomment proof with abc pdr	6 years ago
.gitignore	Makefile: add clean target; fixed Reset_n_i port dir in alu_t.sv	6 years ago
LICENSE.md	Inital commit	6 years ago
README.md	Update link to git repo	6 years ago

README.md

The original repository is located on my own git-server at https://git.goodcleanfun.de/tmeissner/formal_hw_verification

It is mirrored to github with every push, so both should be in sync.

formal_verification

Tests and examples of using formal verification to check correctness of digital hardware designs. All tests are done with SymbiYosys, a front-end for formal verification flows based on Yosys. Some examples use the VHDL/SystemVerilog frontend plugin by Verific which isn't free SW and not included in the free Yosys version. See on the Symbiotic EDA website for more information.

alu

A simple ALU design in VHDL, together with a formal testbench written in SystemVerilog. The testbench contains various simple SVA properties used by assert & cover directives which are proved with the SymbiYosys tool.

counter

A simple counter design in VHDL, together with a formal testbench written in SystemVerilog. The testbench contains various simple SVA properties used by assert & cover directives which are proved with the SymbiYosys tool.

dlatch

A simple test design which generates the Unsupported cell type $dlatchsr error using with Verific plugin.

vai_reg

A simple register file with VAI (valid-accept-interface) which serves as test design to try formal verification of FSMs.