Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

T. Meissner 3c042a168b Remove unused Data_i port from testbench		7 years ago
alu	Makefile: add clean target; fixed Reset_n_i port dir in alu_t.sv	7 years ago
counter	Remove unused Data_i port from testbench	7 years ago
.gitignore	Makefile: add clean target; fixed Reset_n_i port dir in alu_t.sv	7 years ago
LICENSE.md	Inital commit	7 years ago
README.md	Remove gitignore from alu folder; added link to Yosys	7 years ago

README.md

formal_verification

Tests and examples of using formal verification to check correctness of digital hardware designs. All tests are done with SymbiYosys, a front-end for formal verification flows based on Yosys. Some examples use the VHDL/SystemVerilog parser plugin by Verific which isn't free SW and not included in the free Yosys version. See on the Symbiotic EDA website for more information.

alu

A simple ALU design in VHDL, together with a formal testbench written in SystemVerilog. The testbench contains various simple SVA properties used by assert & cover directives which are proved with the SymbiYosys tool.