|T. Meissner fca663d7ac||4 years ago|
|alu||4 years ago|
|.gitignore||4 years ago|
|LICENSE.md||4 years ago|
|README.md||4 years ago|
Tests and examples of using formal verification to check correctness of digital hardware designs. All tests are done with SymbiYosys, a front-end for formal verification flows based on Yosys. Some examples use the VHDL/SystemVerilog parser plugin by Verific which isn't free SW and not included in the free Yosys version. See on the Symbiotic EDA website for more information.
A simple ALU design in VHDL, together with a formal testbench written in SystemVerilog. The testbench contains various simple SVA properties used by assert & cover directives which are proved with the SymbiYosys tool.