Trying to verify Verilog/VHDL designs with formal methods and tools
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T. Meissner fca663d7ac Makefile: add clean target; fixed Reset_n_i port dir in alu_t.sv 3 years ago
alu Makefile: add clean target; fixed Reset_n_i port dir in alu_t.sv 3 years ago
.gitignore Makefile: add clean target; fixed Reset_n_i port dir in alu_t.sv 3 years ago
LICENSE.md Inital commit 3 years ago
README.md Remove gitignore from alu folder; added link to Yosys 3 years ago

README.md

formal_verification

Tests and examples of using formal verification to check correctness of digital hardware designs. All tests are done with SymbiYosys, a front-end for formal verification flows based on Yosys. Some examples use the VHDL/SystemVerilog parser plugin by Verific which isn't free SW and not included in the free Yosys version. See on the Symbiotic EDA website for more information.

alu

A simple ALU design in VHDL, together with a formal testbench written in SystemVerilog. The testbench contains various simple SVA properties used by assert & cover directives which are proved with the SymbiYosys tool.