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gatemate_experiments
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gatemate_experiments/uart_reg/syn/uart_reg.ccf

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Add inital version of uart register test design
2 years ago
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Add uart_loop design to test gatemate fifo & ram primitives
2 years ago
Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations
2 years ago
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blink & uart_reg designs are working now * Yosys with -luttree option seems to generate Verilog netlist which GateMate p_r tool cannot handle correctly * If -luttree option is used you get bitfiles with nearly random behaviour * So, the Yosys -luttree option is removed to get correctly working designs, even that the GateMate documentation recommends to use the option * Result is a design with worse timing, but it's working as desired :) * Add targets to run post-synthesis & post-implementation simulations * Add Verilog test benches for post-syn/post-imp simulations * Remove debug code
2 years ago
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  1. # Configuration for the Gatemate eval board
  2. 

  3. Pin_in   "clk_i"   Loc = "IO_SB_A8" | SCHMITT_TRIGGER=true;
  4. Pin_in   "rst_n_i" Loc = "IO_EB_B0"; # SW3
  5. 

  6. Pin_in   "uart_rx_i"  Loc = "IO_NB_A1"; # PMODA IO3
  7. Pin_out  "uart_tx_o"  Loc = "IO_NB_A0"; # PMODA IO1
  8. 

  9. Pin_out "debug_o[0]" Loc = "IO_NB_A4";
  10. Pin_out "debug_o[1]" Loc = "IO_NB_A5";
  11. Pin_out "debug_o[2]" Loc = "IO_NB_A6";
  12. Pin_out "debug_o[3]" Loc = "IO_NB_A7";
  13. Pin_out "debug_o[4]" Loc = "IO_NB_B4";
  14. Pin_out "debug_o[5]" Loc = "IO_NB_B5";
  15. Pin_out "debug_o[6]" Loc = "IO_NB_B6";
  16. Pin_out "debug_o[7]" Loc = "IO_NB_B7";