tmeissner
/
gatemate_experiments
1
0
Fork 0
Code Issues 0 Pull Requests 0 Projects 0 Releases 0 Wiki Activity
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
27 Commits
2 Branches
209 KiB
 
 
 
 
 
Tree: 0df7a047be
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '0df7a047be'
${ noResults }
gatemate_experiments/uart_reg/syn
T. Meissner 32fa71a90b Increase pll clock to 10 MHz, add uart_loop design to readme 2 years ago
..
Makefile Update uart_reg to full reg file implementation 2 years ago
tb_uart_reg.v Increase pll clock to 10 MHz, add uart_loop design to readme 2 years ago
uart_reg.ccf Add uart_loop design to test gatemate fifo & ram primitives 2 years ago