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gatemate_experiments/uart_reg
T. Meissner 32fa71a90b Increase pll clock to 10 MHz, add uart_loop design to readme 2 years ago
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rtl Increase pll clock to 10 MHz, add uart_loop design to readme 2 years ago
sim Update uart_reg to full reg file implementation 2 years ago
syn Increase pll clock to 10 MHz, add uart_loop design to readme 2 years ago