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2 years ago
2 years ago
  1. -- This design should display incrementing binary numbers
  2. -- at LED1-LED8 of the GateMate FPGA Starter Kit.
  3. library ieee ;
  4. use ieee.std_logic_1164.all;
  5. use ieee.numeric_std.all;
  6. library gatemate;
  7. use gatemate.components.all;
  8. entity blink is
  9. port (
  10. clk_i : in std_logic; -- 10 MHz clock
  11. rst_n_i : in std_logic; -- SW3 button
  12. led_n_o : out std_logic_vector(7 downto 0) -- LED1..LED8
  13. );
  14. end entity blink;
  15. architecture rtl of blink is
  16. signal s_pll_clk : std_logic;
  17. signal s_pll_lock : std_logic;
  18. signal s_clk_cnt : unsigned(19 downto 0);
  19. signal s_clk_en : boolean;
  20. signal s_rst_n : std_logic;
  21. signal s_cfg_end : std_logic;
  22. begin
  23. pll : CC_PLL
  24. generic map (
  25. REF_CLK => "10",
  26. OUT_CLK => "2",
  27. PERF_MD => "ECONOMY"
  28. )
  29. port map (
  30. CLK_REF => clk_i,
  31. CLK_FEEDBACK => '0',
  32. USR_CLK_REF => '0',
  33. USR_LOCKED_STDY_RST => '0',
  34. USR_PLL_LOCKED_STDY => open,
  35. USR_PLL_LOCKED => s_pll_lock,
  36. CLK270 => open,
  37. CLK180 => open,
  38. CLK0 => s_pll_clk,
  39. CLK90 => open,
  40. CLK_REF_OUT => open
  41. );
  42. cfg_end_inst : CC_CFG_END
  43. port map (
  44. CFG_END => s_cfg_end
  45. );
  46. s_rst_n <= rst_n_i and s_pll_lock and s_cfg_end;
  47. process (s_pll_clk, s_rst_n) is
  48. begin
  49. if (not s_rst_n) then
  50. s_clk_cnt <= (others => '0');
  51. elsif (rising_edge(s_pll_clk)) then
  52. s_clk_cnt <= s_clk_cnt + 1;
  53. end if;
  54. end process;
  55. s_clk_en <= s_clk_cnt = (s_clk_cnt'range => '1');
  56. process (s_pll_clk, s_rst_n) is
  57. begin
  58. if (not s_rst_n) then
  59. led_n_o <= x"FE";
  60. elsif (rising_edge(s_pll_clk)) then
  61. if (s_clk_en) then
  62. led_n_o <= led_n_o(6 downto 0) & led_n_o(7);
  63. end if;
  64. end if;
  65. end process;
  66. end architecture;