tmeissner
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gatemate_experiments
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6 Commits (32fa71a90b5ed32d2064a3eafb58f5beb0ab8c18)

Author SHA1 Message Date
  T. Meissner 3cfa3cc72e Add uart_loop design to test gatemate fifo & ram primitives 2 years ago
  T. Meissner a3cabb7747 Refactoring of CC_PLL simulation model 2 years ago
  T. Meissner 3b6a315a0d Add user_components.vhd containing generic RTL modules 2 years ago
  T. Meissner 6cffeef4a5 Rename components.vhd to rtl_components.vhd 2 years ago
  T. Meissner cfa6f88c55 Add simple gatemate primitives simulation components 2 years ago
  T. Meissner b8d8b791dc Initial commit 2 years ago