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tmeissner
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gatemate_experiments
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blink_with_pll
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6 Commits (4cc4aa25e2124b24c9a6baaee2c6fc57bc77738f)
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SHA1
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T. Meissner
3cfa3cc72e
Add uart_loop design to test gatemate fifo & ram primitives
2 years ago
T. Meissner
a3cabb7747
Refactoring of CC_PLL simulation model
2 years ago
T. Meissner
3b6a315a0d
Add user_components.vhd containing generic RTL modules
2 years ago
T. Meissner
6cffeef4a5
Rename components.vhd to rtl_components.vhd
2 years ago
T. Meissner
cfa6f88c55
Add simple gatemate primitives simulation components
2 years ago
T. Meissner
b8d8b791dc
Initial commit
* Add VHDL component library for Gatemate FPGA primitives
2 years ago