tmeissner
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gatemate_experiments
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3 Commits (5d9943c78f40f9a89b9d96e34ed4904fca5d2d8c)

Author SHA1 Message Date
  T. Meissner 6b1b376932 Use speed instead of moderate FPGA speed grade 2 years ago
  T. Meissner 89730f767a Use random stimuli in uart_loop testbench 2 years ago
  T. Meissner 0df7a047be Add uart_trng design 2 years ago