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gatemate_experiments
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2 Commits (61affc8b49c04de7ffcead9e0ba6d7134008f66e)

Author SHA1 Message Date
  T. Meissner 61affc8b49 Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations 3 years ago
  T. Meissner 0e84416a92 Rename uart folder to uart_reg 3 years ago
  T. Meissner 1003634110 Add inital version of uart register test design 3 years ago
  T. Meissner a0fcc51dc8 Add make target to program FPGA 3 years ago
  T. Meissner f28d35d12b Also remove bit file in clean target 3 years ago
  T. Meissner efaca0c912 Add PnR pass and constraint file 3 years ago
  T. Meissner 95887cb31d Add PLL to blink design 3 years ago
  T. Meissner 45ced01c22 Add blink design & simulation 3 years ago