tmeissner
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gatemate_experiments
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1 Commits (a3cabb7747997cd8282e7c388b3f3eb82febb00a)

Author SHA1 Message Date
  T. Meissner 61affc8b49 Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations 2 years ago
  T. Meissner d57f683506 Adapt sim to updated RTL 2 years ago
  T. Meissner 45ced01c22 Add blink design & simulation 2 years ago