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gatemate_experiments
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51
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2
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209 KiB
VHDL
71.6%
Makefile
13.9%
Verilog
8.7%
C
5.4%
Tcl
0.4%
Branch:
main
blink_with_pll
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gatemate_experiments
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uart_trng
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T. Meissner
5d9943c78f
Remove CC_CTRL_END component, use CC_USR_RSTN instead
1 year ago
..
rtl
Remove CC_CTRL_END component, use CC_USR_RSTN instead
1 year ago
sim
Add uart_trng design
2 years ago
sw
Add uart_trng design
2 years ago
syn
Use speed instead of moderate FPGA speed grade
2 years ago