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gatemate_experiments
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gatemate_experiments/lib
T. Meissner 3cfa3cc72e Add uart_loop design to test gatemate fifo & ram primitives 2 years ago
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rtl_components.vhd Add uart_loop design to test gatemate fifo & ram primitives 2 years ago
sim_components.vhd Refactoring of CC_PLL simulation model 2 years ago
user_components.vhd Add uart_loop design to test gatemate fifo & ram primitives 2 years ago