tmeissner
/
gatemate_experiments
1
0
Fork 0
Code Issues 0 Pull Requests 0 Projects 0 Releases 0 Wiki Activity
27 Commits
2 Branches
209 KiB
Tree: 0df7a047be
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '0df7a047be'
${ noResults }
Commit Graph

6 Commits (0df7a047bebf29853504181428c71d950a4f8274)

Author SHA1 Message Date
  T. Meissner 3cfa3cc72e Add uart_loop design to test gatemate fifo & ram primitives 2 years ago
  T. Meissner a3cabb7747 Refactoring of CC_PLL simulation model 2 years ago
  T. Meissner 3b6a315a0d Add user_components.vhd containing generic RTL modules 2 years ago
  T. Meissner 6cffeef4a5 Rename components.vhd to rtl_components.vhd 2 years ago
  T. Meissner cfa6f88c55 Add simple gatemate primitives simulation components 2 years ago
  T. Meissner b8d8b791dc Initial commit 2 years ago