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gatemate_experiments/uart_loop
T. Meissner 0df7a047be Add uart_trng design 2 years ago
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rtl Increase pll clock to 10 MHz, add uart_loop design to readme 2 years ago
sim Increase pll clock to 10 MHz, add uart_loop design to readme 2 years ago
syn Add uart_trng design 2 years ago