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gatemate_experiments/uart_loop/sim
T. Meissner 32fa71a90b Increase pll clock to 10 MHz, add uart_loop design to readme 2 years ago
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Makefile Increase pll clock to 10 MHz, add uart_loop design to readme 2 years ago
tb_uart_loop.vhd Add uart_loop design to test gatemate fifo & ram primitives 2 years ago