29 Commits (7d60f0ae1b073b4a46eb042a7ab28f4733f9d6a1)

Author SHA1 Message Date
  T. Meissner 7d60f0ae1b add simple wishbone master and slave with support of classic single write and read as specified in the wishbone spec b4; add unit tests for wishbone m,aster & slave 10 years ago
  T. Meissner 8369ba705e add tests for new direction generics/parameters 10 years ago
  T. Meissner 5c06158fac add generic G_DATA_DIR to set if we want transfer from LSB to MSB ore vice versa 10 years ago
  T. Meissner 034b10cdc9 change G_SCLK_DIVIDER range start to 6 (lowest working divider value) and adapt assertion to new range 10 years ago
  T. Meissner 4acbb3c425 using osvvm randompkg to randomize stimuli in SimT tests 10 years ago
  T. Meissner 81ed8e8928 moved deleting of vhdl-2008 packaged from clean to distclean target 10 years ago
  T. Meissner d8f1bf228c fixed fileendings of VHDL-2008 packages 10 years ago
  T. Meissner 79cc8ce4b3 add script to download VHDL-2008 proposed packages & patch file for env_c.vhdl to get it compiled by GHDL 10 years ago
  T. Meissner 595cee0200 fixed location of vhdl 2008 package files 10 years ago
  T. Meissner db5dfc76b0 fixed broken test for t_list_queue (data width mismatch) 10 years ago
  T. Meissner 9af05ea4af better comments, add report when wait_cycles() test finished 10 years ago
  T. Meissner 592893ab2b add version 2.1 of OSVVM library; using osvvm randompkg to randomize stimuli in SpiT tests 10 years ago
  T. Meissner 54168ab07e removed, using string function of VHDL-08 instead 10 years ago
  T. Meissner 3dd69f2d16 fixed stopping of clock when all tests are done 10 years ago
  T. Meissner cd72e16a7e removed forgotten references to deleted StringP.vhd package 10 years ago
  T. Meissner 76f15e8c76 integrate VHDL-08 libraries 10 years ago
  T. Meissner 5dd42b80a2 add synthesizable and configurable SPI master component and enhance unit test 10 years ago
  T. Meissner c9fc7388c9 add synthesizable configurable SPI slave component and unit test 10 years ago
  T. Meissner ac5925c717 add synthesizable configurable SPI slave component and unit test 10 years ago
  T. Meissner 389b3470f1 add cpha parameter do spi_master & spi_slave; change unit test to check all combinations of cpol & cpha 10 years ago
  T. Meissner 58478fa5f0 add new SimP package with various general useful testbench procedures like spi master & slave 10 years ago
  T. Meissner 990a511776 compile all packages in library 'libvhdl' now & use the library in the testbenches 10 years ago
  T. Meissner e70325aa62 use new overloaded procedures with added report string parameter 10 years ago
  T. Meissner 1314da2738 add StringP & AssertP source files to Queuet target 10 years ago
  T. Meissner b02ec5e6b5 replaced assert statements by procedures defined in AssertP package 10 years ago
  T. Meissner 97b6596e83 add test for ascending slv; add info about successfully finished simulation 10 years ago
  T. Meissner fe2e5a5c7e added new StringP (string conversion functions) and unit test for it 10 years ago
  T. Meissner faac81128b removed useless v_count variable and replaced it by using i loop variable 10 years ago
  T. Meissner 1b9408fda2 added new queue t_list_queue, implemented as linked list 10 years ago
  T. Meissner f4d72942b0 initial commit of simple queue design file & testbench 10 years ago