Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. entity tb___DUT__ is
  4. end entity tb___DUT__;
  5. architecture sim of tb___DUT__ is
  6. signal clk : std_logic := '1';
  7. signal cycle : natural := 0;
  8. begin
  9. clk <= not clk after 1 ns;
  10. cycle <= cycle + 1 when rising_edge(clk);
  11. DUT : entity work.__DUT__(psl) port map (clk);
  12. end architecture sim;