tmeissner/psl_with_ghdl - psl_with_ghdl - goodcleanfun Gitea

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

vhdl ghdl psl assertions formal yosys

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Add example for |-> (overlapping suffix implication) operator * Add example for |-> operator * Add formal test for |-> operator example * Add |-> to supported list

5 years ago

Change sby task name from prove to bmc (we do bmc, not unbounded prove)

5 years ago

Add example for |-> (overlapping suffix implication) operator * Add example for |-> operator * Add formal test for |-> operator example * Add |-> to supported list

5 years ago

Change sby task name from prove to bmc (we do bmc, not unbounded prove)

5 years ago

Add example for |-> (overlapping suffix implication) operator * Add example for |-> operator * Add formal test for |-> operator example * Add |-> to supported list

5 years ago

Change sby task name from prove to bmc (we do bmc, not unbounded prove)

5 years ago

Add example for |-> (overlapping suffix implication) operator * Add example for |-> operator * Add formal test for |-> operator example * Add |-> to supported list

5 years ago

Change sby task name from prove to bmc (we do bmc, not unbounded prove)

5 years ago

Add example for |-> (overlapping suffix implication) operator * Add example for |-> operator * Add formal test for |-> operator example * Add |-> to supported list

5 years ago

[tasks]
bmc

[options]
depth 25
bmc: mode bmc

[engines]
bmc: smtbmc z3

[script]
bmc: ghdl --std=08 pkg.vhd sequencer.vhd psl_sere_overlapping_suffix_impl.vhd -e psl_sere_overlapping_suffix_impl
prep -top psl_sere_overlapping_suffix_impl

[files]
../src/pkg.vhd
../src/sequencer.vhd
../src/psl_sere_overlapping_suffix_impl.vhd