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@ -16,7 +16,6 @@ vunit issue_vunit (issue(psl)) { |
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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.numeric_std.all; |
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entity issue is |
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@ -28,19 +27,8 @@ end entity issue; |
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architecture psl of issue is |
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component sequencer is |
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generic ( |
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seq : string |
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); |
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port ( |
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clk : in std_logic; |
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data : out std_logic |
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); |
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end component sequencer; |
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signal a, b : std_logic := '1'; |
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begin |
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end architecture psl; |