Add PSL vunit inherit example as ghdl/ghdl#1899 was fixed

* New example of PSL inherit usage
* Add example to formal tests
* Add issue_1899 to issues tests
* Add inherit to README

README.md

@@ -80,6 +80,7 @@ The next lists will grow during further development
 * Partial support of named sequences (some parameter types missing)
 * Partial support of named properties (some parameter types missing)
 * Partial support of PSL `endpoint` (simulation only, in PSL comments)
+* vunit inhiterance (`inherit`, synthesis only)
 
 ### Yosys formal extensions (reference to [Symbiyosys docs](https://symbiyosys.readthedocs.io/en/latest/verilog.html#unconstrained-variables))
 

formal/psl_vunit_inherit.sby

@@ -0,0 +1,19 @@
+[tasks]
+bmc
+
+[options]
+depth 25
+bmc: mode bmc
+
+[engines]
+bmc: smtbmc z3
+
+[script]
+bmc: ghdl --std=08 pkg.vhd sequencer.vhd psl_vunit_inherit.vhd psl_vunit_inherit.psl -e psl_vunit_inherit
+prep -top psl_vunit_inherit
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/psl_vunit_inherit.vhd
+../src/psl_vunit_inherit.psl

formal/tests.mk

@@ -36,6 +36,7 @@ psl_fell \
 psl_onehot \
 psl_onehot0 \
 psl_vunit \
+psl_vunit_inherit \
 yosys_anyconst \
 yosys_anyseq \
 psl_abort

issues/tests.mk

@@ -11,4 +11,5 @@ issue_1372 \
 issue_1591 \
 issue_1658 \
 issue_1832 \
-issue_1850
+issue_1850 \
+issue_1899

src/psl_vunit_inherit.psl

@@ -0,0 +1,23 @@
+vunit psl_vunit_inherit_0_vu {
+  
+  -- Named sequences
+  sequence s_a (boolean data) is {data; data};
+  sequence s_b (boolean data) is {data};
+
+}
+
+
+vunit psl_vunit_inherit_vu (psl_vunit_inherit(beh)) {
+
+  inherit psl_vunit_inherit_0_vu;
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  SERE_0_a : assert always s_a(a) |-> s_b(b);
+
+  -- This assertion holds, similar to SERE_0_a
+  PROP_0_a : assert always {a; a} |-> {b};
+
+}

src/psl_vunit_inherit.vhd

@@ -0,0 +1,33 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+use work.pkg.all;
+
+
+entity psl_vunit_inherit is
+  port (
+    clk : in std_logic
+  );
+end entity psl_vunit_inherit;
+
+
+architecture beh of psl_vunit_inherit is
+
+  signal a, b : std_logic;
+
+begin
+
+
+  --                              012345
+  SEQ_A : sequencer generic map ("--____") port map (clk, a);
+  SEQ_B : sequencer generic map ("_-____") port map (clk, b);
+
+  -- Stop simulation after longest running sequencer is finished
+  -- Simulation only code by using pragmas
+  -- synthesis translate_off
+  stop_sim(clk, 6);
+  -- synthesis translate_on
+
+
+end architecture beh;