5989b1a
(HEAD -> master)
added gpl-v2 license text by
2012-12-08 12:33:31 +0100
b8d183c
declaration of F_CPU now in the makefile, only check in the c-source, if it was forgotten by
2012-10-10 23:01:36 +0200
0caa647
change timespec name from TS_Clk_i to TS_XcClk_i by
2012-09-27 23:03:41 +0200
cb4a735
wrapped gpio pin test code with a a synchronious process, sensitive to XcClk_i by
2012-09-27 23:02:12 +0200
1259f65
bugfix: added 'NET' before the pin names by
2012-09-27 18:34:43 +0200
7c64b1f
initial commit of config folder & makefile for implementation by
2012-09-27 18:27:26 +0200
4cf56d5
added description of the 'cpld' which contains the cpld test design by
2012-09-27 17:10:27 +0200
8c3ed04
new folder 'cpld' with test project to test the CPLD on USB-AVR-CPLD by
2012-09-27 16:02:41 +0200
036068d
added link to the avr folder by
2012-09-26 23:55:22 +0200
12c7b0a
added closing of the image tag by
2012-09-26 23:53:17 +0200
5636bc6
initial commit of the project README file by
2012-09-26 23:51:06 +0200
05322a6
new folder 'avr' with test project to test the AVR on USB-AVR-CPLD by
2012-09-26 23:32:55 +0200
c898a10
(tag: Version_0.1)
initial commit of design rules for manufacturing the pcb at q-print by
2012-09-14 00:36:06 +0200
e0e8b58
update to latest schematic & board revision, now version 0.1 which is manufactured at q-print :) by
2012-09-14 00:34:57 +0200
92866b7
This is the revision, that is manufactured at q-print, v.0.1 by
2012-09-14 00:31:45 +0200
12db9fa
version 0.1: update to major revision of layout by
2012-09-13 02:25:31 +0200
fdfeac2
major revision of board layout by
2012-09-13 02:16:16 +0200
712e94b
added schematic picture by
2012-09-12 15:23:02 +0200
d2b435f
pics folder with some pictures & fotos of the project by
2012-09-12 14:23:42 +0200
e02048d
initial commit of eagle files with additional data by
2012-09-12 11:34:53 +0200