T. Meissner 521998fd8b | 3 years ago | |
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wishbone | 3 years ago | |
LICENSE.md | 3 years ago | |
README.md | 3 years ago |
Verification IPs for simulation & formal verification of various selected protocols. All tests are done with GHDL and SymbiYosys, a front-end for formal verification flows based on Yosys.
Simple VIP for the wishbone bus protocol. At the moment support of classic single read / write cycles only.