cryptography ip-cores in vhdl / verilog
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  1. [![simulation](https://img.shields.io/github/workflow/status/tmeissner/cryptocores/Simulation/master?longCache=true&style=flat-square&label=simulation&logo=Github%20Actions&logoColor=fff)](https://github.com/tmeissner/cryptocores/actions?query=workflow%3ASimulation)
  2. # cryptocores
  3. Cryptography IP-cores & tests written in VHDL / Verilog
  4. The components in this repository are not intended as productional code.
  5. They serve as proof of concept, for example how to implement a pipeline using
  6. only (local) variables instead of (global) signals. Furthermore they were used
  7. how to do a VHDL-to-Verilog conversion for learning purposes.
  8. The testbenches to verify [DES](des/sim/vhdl/), [AES](aes/sim/vhdl/) and [CTR-AES](ctraes/sim/vhdl/) are examples
  9. how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness
  10. of the VHDL implementation.
  11. *HINT:*
  12. The tests of some algorithms use the OSVVM library, which is redistributed as
  13. submodule. To get & initialize the submodule, please use the `--recursive` option
  14. when cloning this repository. Use `git submodule update --recursive` to update the submodule if you already chaked out the main repository.