cryptography ip-cores in vhdl / verilog
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

131 lines
4.3 KiB

  1. -- ======================================================================
  2. -- CBC-AES encryption/decryption
  3. -- Copyright (C) 2021 Torsten Meissner
  4. -------------------------------------------------------------------------
  5. -- This program is free software; you can redistribute it and/or modify
  6. -- it under the terms of the GNU General Public License as published by
  7. -- the Free Software Foundation; either version 2 of the License, or
  8. -- (at your option) any later version.
  9. -- This program is distributed in the hope that it will be useful,
  10. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. -- GNU General Public License for more details.
  13. -- You should have received a copy of the GNU General Public License
  14. -- along with this program; if not, write to the Free Software
  15. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  16. -- ======================================================================
  17. library ieee;
  18. use ieee.std_logic_1164.all;
  19. use ieee.numeric_std.all;
  20. use work.aes_pkg.all;
  21. entity cbcaes is
  22. port (
  23. reset_i : in std_logic; -- low active async reset
  24. clk_i : in std_logic; -- clock
  25. start_i : in std_logic; -- start cbc
  26. mode_i : in std_logic; -- aes-modus: 0 = encrypt, 1 = decrypt
  27. key_i : in std_logic_vector(0 to 127); -- key input
  28. iv_i : in std_logic_vector(0 to 127); -- iv input
  29. data_i : in std_logic_vector(0 to 127); -- data input
  30. valid_i : in std_logic; -- input key/data valid flag
  31. accept_o : out std_logic; -- ready to encrypt/decrypt
  32. data_o : out std_logic_vector(0 to 127); -- data output
  33. valid_o : out std_logic; -- output data valid flag
  34. accept_i : in std_logic
  35. );
  36. end entity cbcaes;
  37. architecture rtl of cbcaes is
  38. signal s_mode : std_logic;
  39. signal s_aes_mode : std_logic;
  40. signal s_start : std_logic;
  41. signal s_key : std_logic_vector(0 to 127);
  42. signal s_aes_key : std_logic_vector(0 to 127);
  43. signal s_iv : std_logic_vector(0 to 127);
  44. signal s_datain : std_logic_vector(0 to 127);
  45. signal s_datain_d : std_logic_vector(0 to 127);
  46. signal s_aes_datain : std_logic_vector(0 to 127);
  47. signal s_aes_dataout : std_logic_vector(0 to 127);
  48. signal s_dataout : std_logic_vector(0 to 127);
  49. begin
  50. s_aes_datain <= iv_i xor data_i when mode_i = '0' and start_i = '1' else
  51. s_dataout xor data_i when s_mode = '0' and start_i = '0' else
  52. data_i;
  53. data_o <= s_iv xor s_aes_dataout when s_mode = '1' and s_start = '1' else
  54. s_datain_d xor s_aes_dataout when s_mode = '1' and s_start = '0' else
  55. s_aes_dataout;
  56. s_aes_key <= key_i when start_i = '1' else s_key;
  57. s_aes_mode <= mode_i when start_i = '1' else s_mode;
  58. inputregister : process (clk_i, reset_i) is
  59. begin
  60. if (reset_i = '0') then
  61. s_mode <= '0';
  62. s_start <= '0';
  63. s_key <= (others => '0');
  64. s_iv <= (others => '0');
  65. s_datain <= (others => '0');
  66. s_datain_d <= (others => '0');
  67. elsif (rising_edge(clk_i)) then
  68. if (valid_i = '1' and accept_o = '1') then
  69. s_start <= start_i;
  70. s_datain <= data_i;
  71. s_datain_d <= s_datain;
  72. if (start_i = '1') then
  73. s_mode <= mode_i;
  74. s_key <= key_i;
  75. s_iv <= iv_i;
  76. end if;
  77. end if;
  78. end if;
  79. end process inputregister;
  80. outputregister : process (clk_i, reset_i) is
  81. begin
  82. if (reset_i = '0') then
  83. s_dataout <= (others => '0');
  84. elsif (rising_edge(clk_i)) then
  85. if (valid_o = '1' and accept_i = '1') then
  86. s_dataout <= s_aes_dataout;
  87. end if;
  88. end if;
  89. end process outputregister;
  90. i_aes : entity work.aes
  91. generic map (
  92. design_type => "ITER"
  93. )
  94. port map (
  95. reset_i => reset_i,
  96. clk_i => clk_i,
  97. mode_i => s_aes_mode,
  98. key_i => s_aes_key,
  99. data_i => s_aes_datain,
  100. valid_i => valid_i,
  101. accept_o => accept_o,
  102. data_o => s_aes_dataout,
  103. valid_o => valid_o,
  104. accept_i => accept_i
  105. );
  106. end architecture rtl;