222 Commits (3de7dd63a953ead42aa834195a62a96cc29abcf1)
 

Author SHA1 Message Date
  T. Meissner 3de7dd63a9 Add CBC-AES VHDL design & synthesis Makefile 4 years ago
  T. Meissner 2a3fae594f Refactor conditions in counter process; add info about submodule update 4 years ago
  T. Meissner 29668c3214 Bump OSVVM to version 2020.12a 4 years ago
  T. Meissner 81df6e0215 Update & restructure DES testbench to use openSSL and random simuli 4 years ago
  T. Meissner b602931174 Fix CTR-init round, set of iv & key in 1st round only. 4 years ago
  T. Meissner 4c3aa07711 Update CTR-AES testbench to use openSSL as reference, unpolished 4 years ago
  T. Meissner 250fbf34b3 Update CI-badge; add hint to VHPIdirect use in *aes testbenches 4 years ago
  T. Meissner 1fdbcb2d5f
Merge pull request #2 from umarcor/ci/update 4 years ago
  umarcor 24bee6a79b ci: update test script 4 years ago
  umarcor 2e20cf9400 ci: add icons/emojis 4 years ago
  umarcor 7835fc5204 readme: use shield/badge from shields.io 4 years ago
  umarcor 17ce27949f ci: rename 'test' workflow to 'Simulation' 4 years ago
  T. Meissner d9d91763bb CTR-AES: Fix counter incr & init; add 1st simple testbench 4 years ago
  T. Meissner 2d708cbb51 Minor update to TDES sim makefile and testbench 4 years ago
  T. Meissner e3e993fe4b Add Makefile for synthesis of CBCTDES 4 years ago
  T. Meissner 7540c3d2bf Add GHA badge 4 years ago
  T. Meissner e9f14349e6
Merge pull request #1 from umarcor/ci/gha 4 years ago
  umarcor d7b39f322e ci: add GitHub Actions workflow 'test' 4 years ago
  umarcor 6ebfd4afe7 aes: fix build arg order 4 years ago
  umarcor 325a08f301 aes: fix VHDL sources order 4 years ago
  T. Meissner 5640e7884b Update CBCDES unit and tests 4 years ago
  T. Meissner a2c530928e Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 4 years ago
  T. Meissner 1850e5c1e3 Add Makefiles for VHDL synthesis of DES & TDES 4 years ago
  T. Meissner 2e48c18741 Some Makefile refactoring 4 years ago
  T. Meissner cc268c2efb Fix osvvm path 4 years ago
  T. Meissner c5a7007ac5 Implement key schedule for AES decryption, unoptimized 4 years ago
  T. Meissner 1dc2fd2458 Use co-sim for descryption tests also 5 years ago
  T. Meissner 51d7b485b9 Make PSL compatible with simulation & synthesis 5 years ago
  T. Meissner 0a7ed338d6 Use co-sim with openSSL to check AES enc VHDL implementation 5 years ago
  T. Meissner d16c247b5c Add OSVVM as submodule 5 years ago
  T. Meissner 491b4df54f Move PSL stuff in generate block; add formal PSL code 5 years ago
  T. Meissner 303bda25e4 Add CTR-AES VHDL design 5 years ago
  T. Meissner dce8396498 Refactoring; remove unused functions 5 years ago
  T. Meissner 50aaca8c6c Fix PSL cover directives 5 years ago
  T. Meissner b7b9f36c9b Add CBCMAC-AES VHDL design 5 years ago
  T. Meissner 28b2cd3856 Implement key schedule for encryption, finally 5 years ago
  T. Meissner b59791e8f3 Move VHDL library files in work directory 6 years ago
  T. Meissner 77f87536c9 FSM optimizations; PSL enhancements 6 years ago
  T. Meissner c400d2ef1b Add PSL checkers, refactoring 6 years ago
  T. Meissner 735c411ff8 First working version of AES enc & dec 6 years ago
  T. Meissner d8ca919f37 Fixed many incorrect implemented functions 6 years ago
  T. Meissner 42a5eb9b1b Minor refactoring & bugfixing 6 years ago
  T. Meissner 27e06dff2c Fix gmul() & (inv)mixcolums() functions 6 years ago
  T. Meissner 517237cfec Created Readme.md file 8 years ago
  T. Meissner 2f91130184 Add remaining AES functions 9 years ago
  T. Meissner 46f1b9295b merge last changes from amc mini repo 10 years ago
  T. Meissner 8a9b30940e integrate s1-s8() into one s() function with additional parameter s_table; convert lower to upper case 10 years ago
  T. Meissner 313a08b6f3 add verilog simulation environment for cbcmac-des 10 years ago
  T. Meissner 4dd3f74d15 Merge branch 'master' of https://github.com/tmeissner/cryptocores 10 years ago
  T. Meissner 918483068b add ITER define; add accept ports to des instance 10 years ago