T. Meissner 3de7dd63a9 | 4 years ago | |
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.github | 4 years ago | |
aes | 4 years ago | |
cbcaes | 4 years ago | |
cbcdes | 4 years ago | |
cbcmac_aes | 4 years ago | |
cbcmac_des | 4 years ago | |
cbctdes | 4 years ago | |
ctraes | 4 years ago | |
des | 4 years ago | |
lib | 4 years ago | |
tdes | 4 years ago | |
.gitignore | 11 years ago | |
.gitmodules | 4 years ago | |
LICENSE.textile | 10 years ago | |
README.md | 4 years ago |
Cryptography IP-cores & tests written in VHDL / Verilog
The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.
The testbenches to verify DES, AES and CTR-AES are examples how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness of the VHDL implementation.
HINT:
The tests of some algorithms use the OSVVM library, which is redistributed as
submodule. To get & initialize the submodule, please use the --recursive
option
when cloning this repository. Use git submodule update --recursive
to update the submodule if you already chaked out the main repository.