cryptography ip-cores in vhdl / verilog
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T. Meissner 3de7dd63a9 Add CBC-AES VHDL design & synthesis Makefile 4 years ago
.github ci: update test script 4 years ago
aes aes: fix build arg order 4 years ago
cbcaes Add CBC-AES VHDL design & synthesis Makefile 4 years ago
cbcdes Update CBCDES unit and tests 4 years ago
cbcmac_aes Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 4 years ago
cbcmac_des Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 4 years ago
cbctdes Add Makefile for synthesis of CBCTDES 4 years ago
ctraes Refactor conditions in counter process; add info about submodule update 4 years ago
des Update & restructure DES testbench to use openSSL and random simuli 4 years ago
lib Bump OSVVM to version 2020.12a 4 years ago
tdes Minor update to TDES sim makefile and testbench 4 years ago
.gitignore added ignore file 11 years ago
.gitmodules Add OSVVM as submodule 4 years ago
LICENSE.textile added GPLv2 license file 10 years ago
README.md Refactor conditions in counter process; add info about submodule update 4 years ago

README.md

simulation

cryptocores

Cryptography IP-cores & tests written in VHDL / Verilog

The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.

The testbenches to verify DES, AES and CTR-AES are examples how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness of the VHDL implementation.

HINT:

The tests of some algorithms use the OSVVM library, which is redistributed as submodule. To get & initialize the submodule, please use the --recursive option when cloning this repository. Use git submodule update --recursive to update the submodule if you already chaked out the main repository.