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cryptography ip-cores in vhdl / verilog
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cryptocores/cbcdes/sim/vhdl/tb_cbcdes.tcl

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moved in seperate directory 'vhdl'
12 years ago
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Update CBCDES unit and tests * Use des from des dir instead of local copies * Adapt testbench to des interface * Add Makefile for VHDL-synthesis
4 years ago
moved in seperate directory 'vhdl'
12 years ago
​
​
​
​
​
Update CBCDES unit and tests * Use des from des dir instead of local copies * Adapt testbench to des interface * Add Makefile for VHDL-synthesis
4 years ago
moved in seperate directory 'vhdl'
12 years ago
​
 
  1. set signals [list]
  2. lappend signals "top.tb_cbcdes.s_reset"
  3. lappend signals "top.tb_cbcdes.s_clk"
  4. lappend signals "top.tb_cbcdes.s_validin"
  5. lappend signals "top.tb_cbcdes.s_acceptin"
  6. lappend signals "top.tb_cbcdes.s_start"
  7. lappend signals "top.tb_cbcdes.s_mode"
  8. lappend signals "top.tb_cbcdes.s_key"
  9. lappend signals "top.tb_cbcdes.s_iv"
  10. lappend signals "top.tb_cbcdes.s_datain"
  11. lappend signals "top.tb_cbcdes.s_validout"
  12. lappend signals "top.tb_cbcdes.s_acceptout"
  13. lappend signals "top.tb_cbcdes.s_dataout"
  14. set num_added [ gtkwave::addSignalsFromList $signals ]