T. Meissner 12 years ago
parent
commit
bab578f2c6
3 changed files with 4 additions and 1 deletions
  1. +2
    -0
      des/rtl/verilog/des.v
  2. +0
    -1
      des/sim/verilog/tb_des.tcl
  3. +2
    -0
      des/sim/verilog/tb_des.v

+ 2
- 0
des/rtl/verilog/des.v View File

@ -19,6 +19,8 @@
// ======================================================================
`timescale 1ns/1ps
module des
(


+ 0
- 1
des/sim/verilog/tb_des.tcl View File

@ -7,5 +7,4 @@ lappend signals "tb_des.key"
lappend signals "tb_des.datain"
lappend signals "tb_des.validout"
lappend signals "tb_des.dataout"
lappend signals "tb_des.outdex"
set num_added [ gtkwave::addSignalsFromList $signals ]

+ 2
- 0
des/sim/verilog/tb_des.v View File

@ -18,6 +18,8 @@
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
// ======================================================================
`timescale 1ns/1ps
module tb_des;


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