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cryptocores
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14 Commits (325a08f3013c5fabacb27b56ab175db0d2005318)

Author SHA1 Message Date
  T. Meissner a2c530928e Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 4 years ago
  T. Meissner 258e9db1e4 removed internal synced copy of reset; set ready to high in reset 11 years ago
  T. Meissner fa93856e07 removed internal synced copy of reset; set ready to high in reset 11 years ago
  T. Meissner 6c705cf64b moved array type definitions out of functions to head of package, instances now also in package head and are constants 11 years ago
  T. Meissner e8aff41e6e bugfixes to make tdes.v core working correctly 12 years ago
  T. Meissner e2225fbbc9 initial commit os TDES verilog design file 12 years ago
  T. Meissner 45403f17d1 import of des verilog design files 12 years ago
  T. Meissner d779f5aebe moved into seperate vhdl folder 12 years ago
  T. Meissner 7822728a74 moved into seperate vhdl folder 12 years ago
  Torsten Meissner 4b8ab0d0cc added async reset to des-module to avoid simulation warnings and unititialized ports 13 years ago
  Torsten Meissner e1c9cb244b fixed some bugs with the key suppliment 13 years ago
  Torsten Meissner aec8130bdc some minor bugfixes 13 years ago
  Torsten Meissner 25f37f7d9e Revision 0.1 2011/10/08 13 years ago
  Torsten Meissner 2a0a9348f3 Revision 0.1 2011/10/08 13 years ago