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cryptocores
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21 Commits (4489748aeca97b55fa91f7871f7ea76606a8610c)

Author SHA1 Message Date
  T. Meissner 4489748aec initial commit os CBCDES verilog design file 12 years ago
  T. Meissner 51745c47d3 adapt to new directory structure 12 years ago
  T. Meissner 8c33d73411 moved in seperate directory 'vhdl' 12 years ago
  T. Meissner cb76c16c7b moved in seperate directory 'vhdl' 12 years ago
  T. Meissner c42beff5b8 moved vhdl design files in directory 'vhdl' 12 years ago
  T. Meissner ab47fd3a54 import verilog des design files from des project 12 years ago
  T. Meissner 6356f624af moved vhdl design files in directory 'vhdl' 12 years ago
  Torsten Meissner 114a4e1072 remove OVL support in older, finished & verified projects 13 years ago
  Torsten Meissner 8fd02d0844 you can now include the OVL library if you set the OVL_ENABLE flag to 1 13 years ago
  Torsten Meissner c5fa11fbef integrated tcl-file into gtkwave starting parameters 13 years ago
  Torsten Meissner 4b8ab0d0cc added async reset to des-module to avoid simulation warnings and unititialized ports 13 years ago
  Torsten Meissner 5f440e10ad Revision 0.2 2011/10/06 13 years ago
  Torsten Meissner 5e4bd28cf1 added basic verification of cbc ability 13 years ago
  Torsten Meissner f0cba7ebb6 expanded simulation time to 220us 13 years ago
  Torsten Meissner 80f6b63062 Revert 32e44bdf948f5fc3a420a37defe918ec55d67b6a^..HEAD 13 years ago
  Torsten Meissner 32e44bdf94 Revision 1.2 2011/10/05 13 years ago
  Torsten Meissner 5b924ff4e2 expanded simulation time to 200 us for decryption testcases 13 years ago
  Torsten Meissner b9ed938d6d register mode_i and iv_i only if start_i is high 13 years ago
  Torsten Meissner 8909aa0d9a expanded simulation time to 100 us for encryption testcases 13 years ago
  Torsten Meissner ec99a6b8eb Revision 1.1 2011/09/25 13 years ago
  Torsten Meissner 5c4b112411 Initial Release of CBC-DES 13 years ago