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cryptocores
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11 Commits (716ce2725bec57e23fe84cc980debb70e3a1fda8)

Author SHA1 Message Date
  T. Meissner f8226943a3 changed reset & clk timing according to vhdl testbench 11 years ago
  T. Meissner e62c0d5916 added verilog simulation environment 11 years ago
  T. Meissner 3afaaaf4b2 finished conversion of vhdl design into verilog 11 years ago
  Torsten Meißner f7eb3587cf adapted paths 11 years ago
  T. Meissner 7105d21c74 iunitial commit os cbctdes verilog sources 11 years ago
  T. Meissner 67fdd7e63b moved in seperate directory 'vhdl' 11 years ago
  T. Meissner 20f0baca10 moved in seperate directory 'vhdl' 11 years ago
  Torsten Meissner 114a4e1072 remove OVL support in older, finished & verified projects 12 years ago
  Torsten Meissner 8fd02d0844 you can now include the OVL library if you set the OVL_ENABLE flag to 1 12 years ago
  Torsten Meissner c5fa11fbef integrated tcl-file into gtkwave starting parameters 13 years ago
  Torsten Meissner 2e7c021255 initial release of tdes in cbc mode 13 years ago