cryptocores

Author	SHA1	Message	Date
T. Meissner	9454ed15cd	removed assignments of c & d in r & l process reset state	10 years ago
T. Meissner	6dd9c4ad6c	removed wrong assignments of r in the c & d process	10 years ago
T. Meissner	b9efb85f01	add second iterative implementation; selection between the two implementations by #ifdef's	10 years ago
T. Meissner	80443e531d	internal mode is now a latched copy of mode_i (ITER)	10 years ago
T. Meissner	034386b0ce	removed forgotten data_o drivers from process	10 years ago
T. Meissner	1e53c62084	data_o is generated in parallel to sync process now	10 years ago
T. Meissner	5ebdae8b61	add iterative implementation; config via generic 'design_type'	10 years ago
T. Meissner	a51f0ef35b	beauty care	11 years ago
T. Meissner	45c9409572	more moving of type & constant definitions to pkg header	11 years ago
T. Meissner	8d0430ac03	moved array type definitions out of functions to head of package, instances now also in package head and are constants	11 years ago
T. Meissner	09da6ae1a6	correct some copy & paste errors in key scheduling process	12 years ago
T. Meissner	4c7037b7c3	added timescale directive and set it to 1 ns/1 ps	12 years ago
T. Meissner	ccf8140132	complete refactoring of the des verilog code * now 2 seperate processes: key scheduling & data path * keys are now concurrent wire assignments	12 years ago
T. Meissner	08f7c16e5d	fixed some errors in des helper functions * functions s1() - s8() returned incorrect slices of the matrix * function s2() had one incorrect nibble in cause of faulty conversion	12 years ago
Torsten Meissner	74c974f956	further converting of vhdl into verilog code	13 years ago
Torsten Meissner	5bf2207f11	splitting function ip to 2 sub functions ip0 & ip1	13 years ago
Torsten Meissner	270ac45e53	began with converting of implementation from vhdl to verilog	13 years ago
Torsten Meissner	3399288adc	change lib path for simulation	13 years ago
Torsten Meissner	804a359af4	new synchronous process for mode & valid signals	13 years ago
Torsten Meissner	e1900a3e28	all necessary functions are complete now	13 years ago
Torsten Meissner	69c7fe92f9	added functions s1 - s8	13 years ago
Torsten Meissner	c1f59849e5	initial release of des function package in verilog	13 years ago
Torsten Meissner	93186c5d1c	initial release of des verilog implementation, framework code only at the moment	13 years ago
Torsten Meissner	7bfc136dda	Revert "dasdsad" This reverts commit `4b41ea24dd`.	13 years ago
Torsten Meissner	4b41ea24dd	dasdsad	13 years ago
Torsten Meissner	1be72c73b6	Revert "New verily top level file of DES algorithm" This reverts commit `3ff9e3e269`.	13 years ago
Torsten Meissner	3ff9e3e269	New verily top level file of DES algorithm	13 years ago
Torsten Meissner	4f5b5a1830	move vhdl files into separate directories	13 years ago
Torsten Meissner	0b1ef754eb	Revert "move vhdl files into separate directory" This reverts commit `fdc730de69`.	13 years ago
Torsten Meissner	fdc730de69	move vhdl files into separate directory	13 years ago
Torsten Meissner	114a4e1072	remove OVL support in older, finished & verified projects	13 years ago
Torsten Meissner	4b8ab0d0cc	added async reset to des-module to avoid simulation warnings and unititialized ports	13 years ago
Torsten Meissner	65aaba575b	initialize all internal variables to 0 to remove numeric_std-lib warnings	13 years ago
Torsten Meissner	f30ba5e180	added ip-core: des algorithm as described in fips document 46-3	13 years ago

34 Commits (9454ed15cd30f93a794de8d2f0561cab92a7ba2e)