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cryptocores
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20 Commits (d3efde11360c6cf9339f7bdca8904f9123022784)

Author SHA1 Message Date
  T. Meissner e8aff41e6e bugfixes to make tdes.v core working correctly 12 years ago
  T. Meissner 5fff1d89d1 initial commit of verilog simulation environment for tdes core 12 years ago
  T. Meissner e2225fbbc9 initial commit os TDES verilog design file 12 years ago
  T. Meissner 45403f17d1 import of des verilog design files 12 years ago
  T. Meissner dd979b5cd3 adapt makefile to new directory structure; new variable SRC_FILES for vhdl sources 12 years ago
  T. Meissner 715b8b1229 beauty care 12 years ago
  T. Meissner 30a7af4830 moved into seperate vhdl folder 12 years ago
  T. Meissner 5e422923cf moved into seperate vhdl folder 12 years ago
  T. Meissner d779f5aebe moved into seperate vhdl folder 12 years ago
  T. Meissner 7822728a74 moved into seperate vhdl folder 12 years ago
  Torsten Meissner 114a4e1072 remove OVL support in older, finished & verified projects 13 years ago
  Torsten Meissner 8fd02d0844 you can now include the OVL library if you set the OVL_ENABLE flag to 1 13 years ago
  Torsten Meissner c5fa11fbef integrated tcl-file into gtkwave starting parameters 13 years ago
  Torsten Meissner 4b8ab0d0cc added async reset to des-module to avoid simulation warnings and unititialized ports 13 years ago
  Torsten Meissner d3314a7d46 minor updates 13 years ago
  Torsten Meissner e1c9cb244b fixed some bugs with the key suppliment 13 years ago
  Torsten Meissner aec8130bdc some minor bugfixes 13 years ago
  Torsten Meissner a288199209 initial release of testbench and makefile 13 years ago
  Torsten Meissner 25f37f7d9e Revision 0.1 2011/10/08 13 years ago
  Torsten Meissner 2a0a9348f3 Revision 0.1 2011/10/08 13 years ago