cryptocores

1.7 MiB

Author	SHA1	Message	Date
T. Meissner	ab47fd3a54	import verilog des design files from des project	12 years ago
T. Meissner	09da6ae1a6	correct some copy & paste errors in key scheduling process	12 years ago
T. Meissner	4c7037b7c3	added timescale directive and set it to 1 ns/1 ps	12 years ago
T. Meissner	ccf8140132	complete refactoring of the des verilog code * now 2 seperate processes: key scheduling & data path * keys are now concurrent wire assignments	12 years ago
Torsten Meissner	74c974f956	further converting of vhdl into verilog code	13 years ago
Torsten Meissner	270ac45e53	began with converting of implementation from vhdl to verilog	13 years ago
Torsten Meissner	3399288adc	change lib path for simulation	13 years ago
Torsten Meissner	804a359af4	new synchronous process for mode & valid signals	13 years ago
Torsten Meissner	c1f59849e5	initial release of des function package in verilog	13 years ago
Torsten Meissner	93186c5d1c	initial release of des verilog implementation, framework code only at the moment	13 years ago
Torsten Meissner	78db757f9d	new verily version of ads, startup code only at the moment	13 years ago