cryptography ip-cores in vhdl / verilog

vhdl ghdl osvvm fpga testbenches verilog cryptography

umarcor d7b39f322e ci: add GitHub Actions workflow 'test'		4 years ago
.github	ci: add GitHub Actions workflow 'test'	4 years ago
aes	aes: fix build arg order	4 years ago
cbcdes	Update CBCDES unit and tests	4 years ago
cbcmac_aes	Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring	4 years ago
cbcmac_des	Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring	4 years ago
cbctdes	removed internal synced copy of reset_i; set ready to high in reset	11 years ago
ctraes	Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring	4 years ago
des	Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring	4 years ago
lib	Add OSVVM as submodule	5 years ago
tdes	Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring	4 years ago
.gitignore	added ignore file	11 years ago
.gitmodules	Add OSVVM as submodule	5 years ago
LICENSE.textile	added GPLv2 license file	10 years ago
README.md	Use co-sim with openSSL to check AES enc VHDL implementation	5 years ago

README.md

cryptocores

cryptography ip-cores in vhdl / verilog

The components in this repository are not intended for productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.

HINT:

The tests of some algorithms use the OSVVM library, which is redistributed as submodule. To get & initialize the submodule, please use the --recursive option when cloning this repository.