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tmeissner
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cryptocores
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3 Commits (d7b39f322e4d4e8f9feed20d6d92c01a658cc757)
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SHA1
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T. Meissner
2a2aa23e21
wait for rising edge of reset before send stimuli data
11 years ago
T. Meissner
f8226943a3
changed reset & clk timing according to vhdl testbench
11 years ago
T. Meissner
e62c0d5916
added verilog simulation environment
11 years ago