This website works better with JavaScript.
Home
Help
Sign In
tmeissner
/
cryptocores
Watch
1
Star
0
Fork
0
Code
Issues
0
Pull Requests
0
Releases
0
Wiki
Activity
cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
157
Commits
1
Branch
1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
Tree:
1e53c62084
master
Branches
Tags
${ item.name }
Create branch
${ searchTerm }
from '1e53c62084'
${ noResults }
HTTPS
ZIP
TAR.GZ
T. Meissner
1e53c62084
data_o is generated in parallel to sync process now
10 years ago
aes
added prototype of addroundkey() function
11 years ago
cbcdes
moved array type definitions out of functions to head of package, instances now also in package head and are constants
11 years ago
cbctdes
removed internal synced copy of reset_i; set ready to high in reset
11 years ago
des
data_o is generated in parallel to sync process now
10 years ago
tdes
added removing of tb_tdes binary and *.o files in clean target
11 years ago
.gitignore
added ignore file
11 years ago