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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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222
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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cryptocores
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ctraes
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rtl
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vhdl
History
T. Meissner
2a3fae594f
Refactor conditions in counter process; add info about submodule update
4 years ago
..
ctraes.vhd
Refactor conditions in counter process; add info about submodule update
4 years ago