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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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195
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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cryptocores
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cbctdes
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History
T. Meissner
a91d55740a
wait for rising edge of s_reset before send stimuli data
11 years ago
..
verilog
wait for rising edge of reset before send stimuli data
11 years ago
vhdl
wait for rising edge of s_reset before send stimuli data
11 years ago