tmeissner
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gatemate_experiments
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4 Commits (6b1b376932b6b309dd293df98c3f3115c102949f)

Author SHA1 Message Date
  T. Meissner 6b1b376932 Use speed instead of moderate FPGA speed grade 2 years ago
  T. Meissner 89730f767a Use random stimuli in uart_loop testbench 2 years ago
  T. Meissner b2e9cf5155 Remove unneeded synthesis attributes for ring oscillator 2 years ago
  T. Meissner 0df7a047be Add uart_trng design 2 years ago