tmeissner
/
gatemate_experiments
1
0
Fork 0
Code Issues 0 Pull Requests 0 Projects 0 Releases 0 Wiki Activity
50 Commits
2 Branches
209 KiB
Tree: bb98b0e5f5
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from 'bb98b0e5f5'
${ noResults }
Commit Graph

5 Commits (bb98b0e5f587d12c55e7f291ce5322ae345553e4)

Author SHA1 Message Date
  T. Meissner 6b1b376932 Use speed instead of moderate FPGA speed grade 2 years ago
  T. Meissner 89730f767a Use random stimuli in uart_loop testbench 2 years ago
  T. Meissner 0df7a047be Add uart_trng design 2 years ago
  T. Meissner 32fa71a90b Increase pll clock to 10 MHz, add uart_loop design to readme 2 years ago
  T. Meissner 3cfa3cc72e Add uart_loop design to test gatemate fifo & ram primitives 2 years ago