tmeissner
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gatemate_experiments
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7 Commits (dfd0a5968e0e2645b94ff532640bfbde894f4f61)

Author SHA1 Message Date
  T. Meissner ee77f92bd3 Add CC_BRAM_20K and CC_BRAM_40K to rtl components package 3 years ago
  T. Meissner 3cfa3cc72e Add uart_loop design to test gatemate fifo & ram primitives 3 years ago
  T. Meissner a3cabb7747 Refactoring of CC_PLL simulation model 3 years ago
  T. Meissner 3b6a315a0d Add user_components.vhd containing generic RTL modules 3 years ago
  T. Meissner 6cffeef4a5 Rename components.vhd to rtl_components.vhd 3 years ago
  T. Meissner cfa6f88c55 Add simple gatemate primitives simulation components 3 years ago
  T. Meissner b8d8b791dc Initial commit 3 years ago