* Add BMC mode to formal tests
* Adapt wishbone simulation testbench to new generics
* Integrate simulation PSL checks in Wishbone components
* Add generic for Simulation PSL checks to Wishbone components

* A lot of new checks are added to WishboneCheckerE unit
  trying to implement the rules of the Wishbone spec.
* An illegal use of the suffix implication instead of logical
  implicationis fixed in WishboneMasterE unit

* Add 1st initial version of WishBone checker unit
* Add Wishbone package with component & type declarations
* Replace WB slave register by dictionary

* New test case of local write & read at same time
* Add check for WB cycle dependent of WB master local write & read

Instead of using directed tests we switch to coverage driven ones
by using OSVVM capabilities.

uint_bitsize(x) is used to calc number of bits needed for slv when
interpreted as natural and result as unsigned vector.

The new checker monitor WishBoneBusMonitorP checks that address & data
on the WishBone bus are equal to the ones wihich were given at the local
port of the WishBoneMasterE unit to initiate the transfer.

By using an actual version of GHDL, we don't need the VHDL-08
proposal libraries anymore. Enough features of VHDL-08 are integrated
in GHDL to compile OSVVM and our testbenches